Software is tested during the software development process to identify and remove errors. Although various software testing techniques are available, in many cases, software may be tested by loading the software onto the memory of an electronic device (also known as a “system under test,” or SUT) and the SUT may be coupled to a testing computer via a test interface (e.g., Joint Test Action Group (JTAG) interface). The testing computer thus is enabled to test the software stored on the SUT by transmitting signals to and receiving signals from the SUT.
In many cases, the testing computer provides a clock signal to the SUT in order to facilitate communications therebetween. To maximize performance, the frequency associated with the clock signal generally is set at the highest possible value that can be sustained by the testing computer/SUT system. However, in some cases, the SUT may enter a power-saving mode in which the voltage usage of the SUT is reduced to a level that is incompatible with the clock signal frequency. As a result of this incompatibility, communications between the SUT and the testing computer may be negatively impacted. A solution is desirable.